Posted 5th January 2021
ITDev recently engaged with an ASIC design company. This blog outlines our verification strategy, and how our knowledge of UVM allowed us to achieve high test coverage in a very short time.
Posted 6th May 2020
Maintaining a neat and tidy desk is something many of us are familiar with. Doing the same for your FPGA repository can be slightly more challenging. Tom reviews 3 approaches with Vivado, capturing ...more
Posted 21st January 2020
As supporters of good engineering practice we provide guidance, coaching, training and, as for all our engineers, design reviews across all projects. This guidance and support is aimed at ...more