Posted 8th September 2023
This IP core is designed to convert video content between Standard Dynamic Range (SDR) and High Dynamic Range (HDR). Able to be loaded with an industry recognised look-up table (LUT), the IP core ...more
Posted 13th June 2023
This blog contains the final steps for adding the minimal IP to send the necessary SYSMON data to the System Controller for controlling the fan on the AMD Versal VPK120 dev board.
Posted 25th May 2023
Whilst developing on an AMD Versal VPK120 you will want to control the fan speed to keep the noise at manageable levels. This guide captures the steps taken to do this using the onboard System ...more
Posted 12th April 2023
Our team of FPGA designers are experienced in AMD, Intel and Lattice devices, from latest ZynqUltraScale+, Cyclone down to Crosslink. If you are working with AMD (Xilinx) or Intel (Altera) reference ...more
Posted 3rd March 2023
We welcome David back from Australia and review some of the actvities we've been engaged with in February 2023.
Posted 20th January 2023
The customer is always right, and he hasn't changed his requirements, but the consultant says they're in constant flux. Who's right? Let's explore further ...
Posted 9th August 2022
Last month we attended the second TechNES FPGA Frontrunners event, here's our write up from the day ...
Posted 28th July 2022
Here's a short report on our attendance at the ECS Taster week Careers Fair On Tues 26th July. A chance to promote industrial opportunties to year 11 students.
